An SET hardened dual-modular majority voter circuit for TMR system

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An SET hardened dual-modular majority voter circuit for TMR system

A Triple-modular redundancy (TMR) system will have a failure if Single Event Transient (SET) faults affect the voter. In this paper, we propose a full SET-tolerance dual-modular majority voter (DMV) circuit for all internal nodes. The DMV consisting of two simplex-modular voters, two inverters, a C-element inverter and a weak keeper is implemented in CMOS 40 nm technology. A novel XOR gate and ...

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Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability...

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Scheduling Considerations for Voter Checking in FPGA-based TMR Systems

Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple Modular Redundancy (TMR) combined with Module-based configuration memory Error Recovery (MER). By triplicating components and voting on their outputs, TMR helps localize the configuration memory errors, and by reconfiguring the faulty compone...

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ژورنال

عنوان ژورنال: IEICE Electronics Express

سال: 2014

ISSN: 1349-2543

DOI: 10.1587/elex.11.20131029